Maurizio Martina
Improving Network-on-Chip-based turbo decoder architectures.
Fri, 05/06/2011 - 15:01 — SomNambulAuthors: Maurizio Martina, Guido Masera
Subjects: Architecture
AbstractIn this work novel results concerning Network-on-Chip-based turbo decoder
architectures are presented. Stemming from previous publications, this work
concentrates first on improving the throughput by exploiting adaptive-bandwidth
reduction techniques. This technique shows in the best case an improvement of
more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders
require higher area than binary ones. This characteristic has the negative
effect of increasing the data width of the network nodes.VLSI Architectures for WIMAX Channel Decoders.
Wed, 01/27/2010 - 16:01 — SomNambulAuthors: Maurizio Martina, Guido Masera
Subjects: Architecture
AbstractThis chapter describes the main architectures proposed in the literature to
implement the channel decoders required by the WiMax standard, namely
convolutional codes, turbo codes (both block and convolutional) and LDPC. Then
it shows a complete design of a convolutional turbo code encoder/decoder system
for WiMax.Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures.
Fri, 09/11/2009 - 19:13 — SomNambulAuthors: Maurizio Martina, Guido Masera
Subjects: Architecture
AbstractThis work proposes a general framework for the design and simulation of
network on chip based turbo decoder architectures. Several parameters in the
design space are investigated, namely the network topology, the parallelism
degree, the rate at which messages are sent by processing nodes over the
network and the routing strategy.
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